The set/reset type flip-flop is triggered to a high state at Q by the "set" signal and holds that value until reset to low by a signal at the Reset input. This can be implemented as a NAND gate latch or a NOR gate latch and as a clocked version.

One disadvantage of the S/R flip-flop is that the input S=R=0 gives ambiguous results and must be avoided. The J-K flip-flop gets around that problem.

Flip-Flops
Index

Electronics concepts

Digital circuits
 
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Switch Debouncing

Set-Resed Flip-FlopNAND-gate Latch
Index

Electronics concepts

Digital circuits

Reference
Tocci, Digital Systems
Ch 5
 
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